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APPLICATION NOTE
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
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Product Specification
Features
* * * Industry's first TotalCMOSTM PLD - both CMOS design and process technologies Fast Zero Power (FZPTM) design technique provides ultra-low power and very high speed 3V, In-System Programmable (ISP) using a JTAG interface - On-chip superVoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms - Four pin JTAG interface (TCK, TMS, TDI, TDO) - JTAG commands include: Bypass, Idcode High speed pin-to-pin delays of 7.5 ns Ultra-low static power of less than 100 A 5V tolerant I/Os to support mixed Voltage systems 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Up to 12 clocks with programmable polarity at every macrocell Support for complex asynchronous clocking Innovative XPLATM architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed Logic expandable to 37 product terms Advanced 0.35 E2CMOS process Security bit prevents unauthorized access Design entry and verification using industry standard and Xilinx CAE tools Reprogrammable using industry standard device programmers Innovative Control Term structure provides either sum terms or product terms in each logic block for: - Programmable 3-state buffer - Asynchronous macrocell register preset/reset - Up to two asynchronous clocks Programmable global 3-state pin facilitates bed of nails' testing without using logic resources Available in PLCC, VQFP, and Chip Scale BGA packages Industrial grade operates from 2.7V to 3.6V
Description
The XCR3064A CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunnerTM CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR3064A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 A at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 1.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.0 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The XCR3064A CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site).
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* * *
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The XCR3064A CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BPMicrosystems, SMS, and others. The XCR3064A also includes an industry-standard, IEEE 1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the device are supported. 16 macrocells. The six control terms can individually be configured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. In addition, two of the control terms can be used as clock signals (see Macrocell Architecture Section for details). The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. Each macrocell has five dedicated product terms from the PAL array. The pin-to-pin tPD of the XCR3064A device through the PAL array is 7.5 ns. If a macrocell needs more than five product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 1.5 ns. So the total pin-to-pin tPD for the XCR3064A using six to 37 product terms is 9.0 ns (7.5 ns for the PAL + 1.5 ns for the PLA).
XPLA Architecture
Figure 1 shows a high level block diagram of a 64 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunnerTM family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and
MC0 MC1 I/O MC15 16 16 ZIA MC0 MC1 I/O MC15 16 16 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK
MC0 MC1 I/O MC15
MC0 MC1 I/O MC15
SP00439
Figure 1: Xilinx XPLA CPLD Architecture
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36 ZIA INPUTS
CONTROL 5
6
PAL ARRAY
PLA ARRAY
(32) SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
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TO 16 MACROCELLS
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the CoolRunner XCR3064A. The macrocell can be configured as either a D- or T-type flip-flop or a combinatorial logic function. A D-type flip-flop is generally more useful for implementing state machines and data buffering while a T-type flip-flop is generally more useful in implementing counters. Each of these flip-flops can be clocked from any one of six sources. Four of the clock sources (CLK0, CLK1, CLK2, CLK3) are connected to low-skew, device-wide clock networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges. Clock 0 (CLK0) is designated as a "synchronous" clock and must be driven by an external source. Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can be used as "synchronous" clocks that are driven by an external source, or as "asynchronous" clocks that are driven by a macrocell equation. CLK0, CLK1, CLK2, and CLK3 can clock the macrocell flip-flops on either the rising edge or the falling edge of the clock signal. The other clock sources are two of the six control terms (CT2 and CT3) provided in each logic block. These clocks can be individually configured as either a PRODUCT term or SUM term equation created from the 36 signals available inside the logic block. The timing for asynchronous and control term clocks is different in that the tCO time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the tSU time is reduced. P The six control terms of each logic block are used to control the asynchronous Preset/Reset of the flip-flops and the enable/disable of the output buffers in each macrocell. Control terms CT0 and CT1 are used to control the asynchronous Preset/Reset of the macrocell's flip-flop. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied, and that the Preset/Reset feature for each macrocell can also be disabled. Control terms CT2 and CT3 can be used as a clock signal to the flip-flops of the macrocells, and as the Output Enable of the macrocell's output buffer. Control terms CT4 and CT5 can be used to control the Output Enable of the macrocell's output buffer. Having four dedicated Output Enable control terms ensures that the CoolRunnerTM devices are PCI compliant. The output buffers can also be always enabled or always disabled. All CoolRunnerTM devices also provide a Global 3-State (GTS) pin, which, when enabled and pulled Low, will 3-state all the outputs of the device. This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails Testing".
TO ZIA
PAL PLA D/T INIT (P or R) CT0 CT1 GND Q
CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3
GTS GND
CT4 CT5 V CC GND SP00558
Figure 3: XCR3064A Macrocell Architecture There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin feedback path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the DS037 (v1.1) February 10, 2000 output buffer will be 3-stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated (see the section on "Terminations" on page 8 in this data sheet and the application note Terminating Unused I/O Pins in Xilinx XPLA1 and XPLA2 CoolRunnerTM CPLDs). 4
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including tPD, tSU, and tCO. In other architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. For example, in the XCR3064A device, the user knows up front that if a given output uses 5product terms or less, the tPD = 7.5 ns, the tSU_PAL = 3.5 ns, and the tCO = 5.5 ns. If an output is using six to 37 product terms, an additional 1.5 ns must be added to the tPD and tSU timing parameters to account for the time to propagate through the PLA array.
INPUT PIN
tPD_PAL = COMBINATORIAL PAL ONLY tPD_PLA = COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED tSU_PAL = PAL ONLY tSU_PLA = PAL + PLA
D
Q
REGISTERED tCO
OUTPUT PIN
GLOBAL CLOCK PIN
SP00441
Figure 4: CoolRunner Timing Model
TotalCMOS Design Technique for Fast Zero Power
Xilinx is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 1 showing the ICC vs. Frequency of our XCR3064A TotalCMOS CPLD. (Data taken with four up/down loadable 16-bit counters at 3.3V, 25C)
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45 40 35 30 25 ICC (mA) 20 15 10 5 0 TYPICAL
1
20
40
60
80
100
120
140
FREQUENCY (MHz) SP00700
Figure 5: ICC vs. Frequency at VCC = 3.3 V, 25C Table 1: ICC vs. Frequency (VCC = 3.3 V, 25C) Frequency (MHz) Typical ICC (mA) 0 0.03 1 0.3 20 4.7 40 9.4 60 14.0 80 18.7 100 23.2 120 27.7 140 32.4
JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary Scan Test (BST) feature defined for integrated circuits by IEEE Standard 1149.1. This standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of specialized test equipment. The Xilinx XCR3064A devices use the JTAG interface for In-System Programming/Reprogramming. Although only a subset of the full JTAG command set is implemented (see Table 2), the devices are fully capable of sitting in a JTAG scan chain. The Xilinx XCR3064A's JTAG interface includes a TAP Port defined by the IEEE 1149.1 JTAG Specification. As implemented in the Xilinx XCR3064A, the TAP Port includes four of the five pins (refer to Table 4) described in the JTAG specification: TCK, TMS, TDI, and TDO. The fifth signal defined by the JTAG specification is TRST* (Test Reset). TRST* is considered an optional signal, since it is not actually required to perform BST or ISP. The Xilinx XCR3064A saves an I/O pin for general purpose use by not implementing the optional TRST* signal in the JTAG interface. Instead, the Xilinx XCR3064A supports the test reset functionality through the use of its power up reset circuit, which is included in all Xilinx CPLDs. The pins associated with the TAP Port should connect to an external pull-up DS037 (v1.1) February 10, 2000
resistor to keep the JTAG signs from floating when they are not being used. In the Xilinx XCR3064A, the four mandatory JTAG pins each require a unique, dedicated pin on the device. The devices come from the factory with these I/O pins set to perform JTAG functions, but through the software, the final function of these pins can be controlled. If the end application will require the device to be reprogrammed at some future time with ISP, then the pins can be left as dedicated JTAG functions, which means they are not available for use as general purpose I/O pins. However, unlike some other CPLDs, the Xilinx XCR3064A allow the macrocells associated with these pins to be used as buried logic when the JTAG/ISP function is enabled. This is the default state for the software, and no action is required to leave these pins enabled for the JTAG/ISP functions. If, however, JTAG/ISP is not required in the end application, the software can specify that this function be turned off and that these pins be used as general purpose I/O. Because the devices initially have the JTAG/ISP functions enabled, the JEDEC file can be downloaded into the device once, after which the JTAG/ISP pins will become general purpose I/O. This feature is good for manufacturing because the devices can be programmed during test and assembly of the end product and yet still use all of the I/O pins after the programming is
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done. It eliminates the need for a costly, separate programming step in the manufacturing process. Of course, if the JTAG/ISP function is never required, this feature can be turned off in the software and the device can be programmed with an industry-standard programmer, leaving the pins available for I/O functions. Table 3 defines the dedicated pins used by the four mandatory JTAG signals for each of the XCR3064A package types.
Table 2: XCR3064A Low-Level JTAG Boundary-Scan Commands Instruction (Instruction Code) Register Used Bypass (1111) Bypass Register Idcode (0001) Boundary-Scan Register Description Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. The Bypass instruction can be entered by holding TDI at a constant high value and completing an Instruction-Scan cycle. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of the components assembled onto a printed circuit board. Thus, in circumstances where the component population may vary, it is possible to determine what components exist in a product.
Table 3: JTAG Pin Description Pin TCK TMS TDI TDO Name Test Clock Output Test Mode Select Test Data Input Test Data Output Description Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively. Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode operation. Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK. Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The signal is tri-stated if data is not being shifted out of the device.
Table 4: XCR3064A JTAG Pinout by Package Type Device XCR3064A 44-pin PLCC 44-pin VQFP 56-ball CSP 100-pin VQFP (Pin Number/Macrocell #) TMS TDI 13/B15 7/A8 7/B15 1/A8 G1/B15 C1/A8 15/B15 4/A8
TCK 32/C15 26/C15 F10/C15 62/C15
TDO 38/D8 32/D8 C10/D8 73/D8
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ISP is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment to the end customer. ISP provides substantial benefits in each of the following areas: * Design * * Faster time-to-market Debug partitioning and simplified prototyping Printed circuit board reconfiguration during debug Better device and board level testing Multi-Functional hardware Reconfigurability for test Eliminates handling of "fine lead-pitch" components for programming Reduced Inventory and manufacturing costs Improved quality and reliability Easy remote upgrades and repair Support for field configuration, reconfiguration, and customization pins when fabricating a PC board. Allowing unused inputs and I/O pins to float can cause the voltage to be in the linear region of the CMOS input structures, which can increase the power consumption of the device. The XCR3064A CPLDs have programmable on-chip pull-down resistors on each I/O pin. These pull-downs are automatically activated by the fitter software for all unused I/O pins. Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any unused I/O pins on the XCR3064A device be left unconnected. There are no on-chip pull-down structures associated with the dedicated input pins. Xilinx recommends that any unused dedicated inputs be terminated with external 10k pull-up resistors. These pins can be directly connected to VCC or GND, but using the external pull-up resistors maintains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes. When using the JTAG/ISP functions, it is also recommended that 10k pull-up resistors be used on each of the pins associated with the four mandatory JTAG signals. Letting these signals float can cause the voltage on TMS to come close to ground, which could cause the device to enter JTAG/ISP mode at unspecified times. See the application notes JTAG and ISP Overview for Xilinx XPLA1 and XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx XPLA1 and XPLA2 CoolRunner CPLDs for more information.
Manufacturing
Field Support
The Xilinx XCR3064A allows for 3.3V, in-system programming/reprogramming of its EEPROM cells via its JTAG interface. An on-chip charge pump eliminates the need for externally-provided superVoltages, so that the XCR3064A may be easily programmed on the circuit board using only the 3V supply required by the device for normal operation. A set of low-level ISP basic commands implemented in the XCR3064A enable this feature. The ISP commands implemented in the Xilinx XCR3064A are specified in Table 5 Please note that an ENABLE command must precede all ISP commands unless an ENABLE command has already been given for a preceding ISP command.
JTAG and ISP Interfacing
A number of industry-established methods exist for JTAG/ISP interfacing with CPLDs and other integrated circuits. The XCR3064A supports the following methods: * * * * * * PC parallel port Workstation or PC serial port Embedded processor Automated test equipment Third party programmers High-End ISP Tools
Terminations
The CoolRunner XCR3064A CPLDs are TotalCMOS devices. As with other CMOS devices, it is important to consider how to properly terminate unused inputs and I/O Table 5: Low Level ISP Commands Instruction Instruction Code (Register Used) Enable 1001 (ISP Shift Register) Erase 1010 (ISP Shift Register) Program 1011 (ISP Shift Register) Verify 1100 (ISP Shift Register)
Description Enables the Erase, Program, and Verify commands. Erases the entire EEPROM array. Programs the data in the ISP Shift Register into the addressed EEPROM row. Transfers the data from the addressed row to the ISP Shift Register. The data can then be shifted out and compared with the JEDEC file. The outputs during this operation can be defined by the user. www.xilinx.com 1-800-255-7778 8
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Programming Specifications
Symbol Parameter DC Parameters VCCP VCC supply program/verify ICCP ICC limit program/verify VIH Input Voltage (High) VIL Input Voltage (Low) VSOL Output Voltage (Low) Output Voltage (High) VSOH TDO_IOL Output current (Low) TDO_IOH Output current (High) AC Parameters fMAX TCK maximum frequency PWE Pulse width erase PWP Pulse width program PWV Pulse width verify INIT Initialization time TMS_SU TMS setup time before TCK TDI_SU TDI setup time before TCK TMS_H TMS hold time after TCK TDI_H TDI hold time after TCK TDO_CO TDO valid after TCK Min. 3.0 2.0 0.8 0.5 2.4 8 8 10 100 10 10 100 10 10 25 25 40 Max. 3.6 200 Unit V mA V V V V mA mA MHz ms ms s s ns ns ns ns ns
ABSOLUTE MAXIMUM RATINGS1
Symbol VCC VI VOUT IIN TJ Tstr
Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. The chip supply voltage must rise monotonically.
Parameter Supply Voltage2 Input Voltage Output Voltage Input current Maximum junction temperature Storage temperature
Min. -0.5 -1.2 -0.5 -30 -40 -65
Max. 4.6 5.75 VCC +0.5 30 150 150
Unit V V V mA
C C
Operating Range
Product Grade Commercial Industrial 9 Temperature 0 to +70C -40 to +85C www.xilinx.com 1-800-255-7778 Voltage 3.0 to 3.6V 2.7 to 3.6V DS037 (v1.1) February 10, 2000
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DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0C TAMB +70C; 3.0V VCC 3.6V Symbol Parameter VIL Input Voltage low VIH VI VOL VOH II IOZ ICCQ1 ICCD1, 2 IOS CIN CCLK CI/O
Notes: 1. See Table 1 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 3. This parameter guaranteed by design and characterization, not by test.
Test Conditions VCC = 3.0V VCC = 3.6V VCC = 3.0V, IIN = -18 mA VCC = 3.0V, IOL = 12 mA VCC = 3.0V, IOH = -12 mA VIN = 0 to 5.5 V VIN = 0 to 5.5 V VCC = 3.6V, TAMB = 0C VCC = 3.6V, TAMB = 0C at 1 MHz VCC = 3.6V, TAMB = 0C at 50 MHz One pin at a time for no longer than 1 second TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz
Min. 2.0
Max. 0.8 -1.2 0.5
Unit V V V V V A A A mA mA mA pF pF pF
Input Voltage high Input clamp Voltage3 Output Voltage low Output Voltage high Input leakage current 3-stated output leakage current Standby current Dynamic current Short circuit output current3 Input pin capacitance3 Clock input capacitance3 I/O pin capacitance3
2.4 -10 -10
-50
10 10 80 1 25 -200 8 12 10
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AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0C TAMB +70C; 3.0V VCC 3.6V Symbol tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR
Notes: 1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5 pF.
Min. Propagation delay time, input (or feedback node) to output through PAL 2 Propagation delay time, input (or feedback node) to output through 3 PAL + PLA Clock to out (global synchronous clock from pin) 2 Setup time (from input or feedback node) through PAL 3.5 Setup time (from input or feedback node) through PAL + PLA 5 Hold time2 Clock High time2 2 Clock Low time2 2 Input Rise time2 Input Fall time2 Maximum FF toggle rate2 (1/tCH + tCL) 250 Maximum internal frequency2 (1/tSUPAL + tCF) 143 Maximum external frequency2 (1/tSUPAL + tCO) 111 Output buffer delay time2 Input (or feedback node) to internal feedback node delay time through PAL2 Input (or feedback node) to internal feedback node delay time through PAL+PLA2 Clock to internal feedback node delay time2 Delay from valid VCC to valid reset2 Input to output disable2, 3 Input to output valid2 Input to register preset2 Input to register reset2
Parameter
7 Max. 7.5 9 5.5 Min. 2 3 2 5 6.5 2.5 2.5 100 100 200 105 83 2 5.5 7 3.5 20 8 8 9 9
10 Max. 10 11.5 7
Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
0
0
100 100
2 8 9.5 4.5 20 9.5 9.5 9.5 9.5
s
ns ns ns ns
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DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40C TAMB +85C; 2.7V VCC 3.6V Symbol VIL VIH VI VOL VOH II IOZ ICCQ1 ICCD1, 2 IOS CIN CCLK CI/O
Notes: 1. See Table 1 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 3. This parameter guaranteed by design and characterization, not by test.
Parameter Input Voltage low Input Voltage high Input clamp Voltage3 Output Voltage low Output Voltage high Input leakage current 3-stated output leakage current Standby current Dynamic current Short circuit output current3 Input pin capacitance3 Clock input capacitance3 I/O pin capacitance3
Test Conditions VCC = 2.7V VCC = 3.6V VCC = 2.7V, IIN = -18 mA VCC = 2.7V, IOL = 8 mA VCC = 3.0V, IOL = 12 mA VCC = 2.7V, IOH = -8 mA VCC = 3.0V, IOH = -12 mA VIN = 0 to 5.5V VIN = 0 to 5.5V VCC = 3.6V, TAMB = -40C VCC = 3.6V, TAMB = -40C at 1 MHz VCC = 3.6V, TAMB = -40C at 50 MHz One pin at a time for no longer than 1 second TAMB = 25C, f = 1MHz TAMB = 25C, f = 1MHz TAMB = 25C, f = 1MHz
Min. 2.0
Max. 0.8 -1.2 0.5 0.5
2.4 2.4 -10 -10
-50
10 10 100 1 25 -230 8 12 10
Unit V V V V V V V A A A mA mA mA pF pF pF
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AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40C TAMB +85C; 2.7V VCC 3.6V Symbol tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR
Notes: 1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5 pF.
Min. Propagation delay time, input (or feedback node) to output through PAL 2 Propagation delay time, input (or feedback node) to output through 3 PAL + PLA Clock to out (global synchronous clock from pin) 2 Setup time (from input or feedback node) through PAL 5 Setup time (from input or feedback node) through PAL + PLA 6.5 Hold time2 Clock High time 3 Clock Low time 3 Input Rise time Input Fall time Maximum FF toggle rate2 (1/tCH + tCL) 166 Maximum internal frequency2 (1/tSUPAL + tCF) 111 Maximum external frequency2 (1/tSUPAL + tCO) 90 Output buffer delay time2 Input (or feedback node) to internal feedback node delay time through PAL2 Input (or feedback node) to internal feedback node delay time through PAL+PLA2 Clock to internal feedback node delay time2 Delay from valid VCC to valid reset2 Input to output disable2, 3 Input to output valid2 Input to register preset2 Input to register reset2
Parameter
10 Max. 10 11.5 7 Min. 2 3 2 6 7.5 3.5 3.5 100 100 143 95 77 2 8 9.5 5 20 10 10 10 10
12 Max. 12 13.5 8
Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
0
0
100 100
2 9 10.5 5.5 20 12 12 12 12
13
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
VCC
S1
Component R1 R2
R1
Values 390 390 35pF
C1
VIN VOUT
Measurement
R2 C1
S1 Open Closed Closed
S2 Closed Open Closed
tPZH tPZL tP
S2
NOTE: For tPHZ and tPLZ C = 5 pF, and 3-state levels are measured 0.5V from steady-state active level.
SP00461B
5.9
VCC = 3.3 V, 25C
+3.0V 90%
5.8
10% 0V
5.7
tR 1.5ns tF 1.5ns
5.6 tPD_PAL (ns) 5.5
SP00368 MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
5.4
Figure 7: Voltage Waveform
5.3
Table 6: tPD_PAL vs # of Outputs Switching (VCC = 3.3 V, T = 25C) # of Outputs Typical (ns) 1 5.3 2 5.3 4 5.4 8 5.6 12 5.7 16 5.9
5.2 1 2 4 8 12 16 NUMBER OF OUTPUTS SWITCHING
SP00639
Figure 6: tPD_PAL vs. Output Switching DS037 (v1.1) February 10, 2000 www.xilinx.com 1-800-255-7778 14
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
Pin Function and Layout
XCR3064 44-Pin PLCC and VQFP Package
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PLCC IN1 IN3 VCC I/O-A0-CK3 I/O-A2 I/O-A5 I/O-A8 I/O-A11 I/O-A12 GND I/O-A13 I/O-A15 I/O-B15 (TMS) I/O-B13 VCC I/O-B10 I/O-B8 I/O-B4 I/O-B3 I/O-B2 I/O-B0/CK2 GND VQFP I/O-A8 (TDI) I/O-A11 I/O-A12 GND I/O-A13 I/O-A15 I/O-B15 (TMS) I/O-B13 VCC I/O-B10 I/O-B8 I/O-B4 I/O-B3 I/O-B2 I/O-B0/CK2 GND VCC I/O-B0/CK1 I/O-C2 I/O-C3 I/O-C4 I/O-C7 Pin # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PLCC VCC I/O-C0/CK1 I/O-C2 I/O-C3 I/O-C4 I/O-C7 I/O-C8 GND I/O-C13 I/O-C15 (TCK) I/O-D15 I/O-D13 VCC I/O-D12 I/O-D11 I/O-D8 (TDO) I/O-D7 I/O-D2 I/O-D0 GND I/O-CK0 IN2-gtsn VQFP I/O-C8 GND I/O-C13 I/O-C15 (TCK) I/O-D15 I/O-C13 VCC I/O-D12 I/O-D11 I/O-D8 (TDO) I/O-D7 I/O-D2 I/O-D0 GND IN0/CK0 IN2-gtsn IN1 IN3 VCC
I/O-A0-CK3
I/O-A2 I/O-A5
XCR3064A: 44-pin PLCC
XCR3064A: 44-pin VQFP
6
1
40
44
34
7
39
1
33
PLCC
VQFP
17
29
11
23
18
28
12
22
15
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DS037 (v1.1) February 10, 2000
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking XCR3064A - 56-Ball Chip Scale BGA
Pkg Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B10 C1 C3 C4 C5 C6 C7 C8 C10 Function I/O-A3 I/O-A5 I/O-A7 VCC I/O-D4 IN0/CK0 GND I/O-D2 I/O-D3 I/O-D6 I/O-A4 I/O-D7 I/O-A8 (TDI) I/O-A2 I/O-A0/CK3 IN3 IN1 IN2-GTSN I/O-D0 I/O-D8 (TDO) Pkg Ball D1 D3 D8 D10 E1 E3 E8 E10 F1 F3 F8 F10 G1 G3 G8 G10 Function I/0-A11 I/0-A12 I/0-D11 VCC GND I/0-A13 I/0-D13 I/0-D15 I/0-A15 I/0-B13 I/0-D13 I/0-C15(TCK) I/O-B15(TMS) I/O-B11 I/O-C13 GND Pkg Ball H1 H3 H4 H5 H6 H7 H8 H10 J1 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 Function VCC I/O-B3 I/O-B2 VCC I/O-C2 I/O-C3 I/O-C4 I/O-C11 I/O-B10 I/O-C5 I/O-B8 I/O-B5 I/O-B4 I/O-B7 I/O-C0/CK2 GND I/O-C0/CK1 I/O-C10 I/O-C7 I/O-C8
XCR3064A: 56-ball Chup Scale BGA
XCR3064A: 100-pin VQFP
A1 BALL PAD CORNER 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K
100
76
1
75
VQFP
25
51
26
50
BOTTOM VIEW sp00674a
DS037 (v1.1) February 10, 2000
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking XCR3064A - 100-pin VQFP Package
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Function I/O-A6 I/O-A7 VCC I/O-A8 (TDI) NC I/O-A9 NC I/O-A10 I/O-A11 I/O-A12 GND I/O-A13 I/O-A14 I/O-A15 I/O-B15 (TMS) I/O-B14 I/O-B13 VCC I/O-B12 I/O-B11 I/O-B10 NC I/O-B9 NC I/O-B8 GND NC NC I/O-B7 I/O-B6 I/O-B5 I/O-B4 I/O-B3 VCC I/O-B2 I/O-B1 I/O-B0/CK2 GND VCC I/O-C0/CK1 I/O-C1 I/O-C2 Pin # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Function GND I/O-C3 I/O-C4 I/O-C5 I/O-C6 I/O-C7 NC NC VCC I/O-C8 NC I/O-C9 NC I/O-C10 I/O-C11 I/O-C12 GND I/O-C13 I/O-C14 I/O-C15 (TCK) I/O-D15 I/O-D14 I/O-D13 VCC I/O-D12 I/O-D11 I/O-D10 NC I/O-D9 NC I/O-D8 (TDO) GND I/O-D7 I/O-D6 NC NC I/O-D6 I/O-D4 I/O-D3 VCC I/O-D2 I/O-D1 Pin # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 -
-
-
-
Function I/O-D0 GND IN0/CK0 IN2-gtsn IN1 IN3 VCC I/O-A0/CK3 I/O-A1 I/O-A2 GND I/O-A3 I/O-A4 I/O-A5 NC NC -
17
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
Ordering Information
Example: XCR3064A -7 PC 44 C
Device Type Speed Options Temperature Range Number of Pins Package Type
Speed Options -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay -7: 7.5 ns pin-to-pin delay
Temperature Range C = Commercial, TA = 0C to +70C I = Industrial, TA = -40C to +85C Packaging Options VQ44: 44-pin VQFP PC44: 44-pin PLCC CP56: 56-ball Chip Scale VQ100: 100-pin VQFP
Component Availability
Pins Type Code XCR3064A 44 Plastic VQFP VQ44 I C, I C Plastic PLCC PC44 I C, I C 56 Plastic csp CP56 I C, I C 100 Plastic PQFP VQ100 I C, I C
-12 -10 -7
Revision History
Date 9/16/99 2/7/00 Version # 1.0 1.1 Revision Initial Xilinx release. Converted to Xilinx format and updated.
DS037 (v1.1) February 10, 2000
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